Circuit designers have at their disposal, a variety of different methods of implementing their circuit designs. One method involves incorporating their designs in dedicated custom integrated circuits (ICs). The initial cost is relatively high and the turn-around time for producing a first set of these semiconductor chips is relatively long. Another method involves the implementation of application-specific integrated circuits (ASICs). Time to market for ASICs are faster, and it is easier to implement design changes. A third alternative, which enjoys growing popularity, is utilizing programmable logic devices (PLDs).
A PLD is a semiconductor chip that contains an array of gates having programmable interconnections. The gates are programmed according to the specification provided by the circuit designer, thereby resulting in the desired logic functions. The programming usually involves using a piece of hardware, known as a programmer. A programmer is typically coupled via a serial port to a microcomputer, on which some form of programmer software is run. The simplest kind of software enables a designer to select which fuses to burn. The designer decides the desired logic function, at the gate level, then lists the corresponding fuses. Other more sophisticated programmers allow designers to specify Boolean expressions or truth tables. The software handles the minimization, simulation, and programming steps automatically. This yields custom combination and even sequential logic on a PLD chip.
There are basically two variants of PLDs: programmable array logic (PALs) and programmable logic arrays (PLAs). They are available in both bipolar and CMOS construction. PALs use fusible-link (one-time-programmable), whereas PLAs use floating-gate MOS (ultraviolet or electrically erasable). The differences between them are in respect to programming flexibility. PALs are typically faster, cheaper, and easier to program, but PLAs are more flexible. Programming of both types of devices is limited by their built-in structure.
In both cases, the desired logic functions are implemented by using standard product terms (p-terms). This involves first performing an AND function on the input variables and then forming the sum of the products, usually by performing an OR function. Typically, a standard number of p-terms are input to a programmable output structure, known as a macrocell.
One disadvantage with typical prior art PLDs is that logic functions occasionally require more p-terms than the standard PLD device can accommodate. For example, a given macrocell having a maximum of 8 p-terms assigned per macrocell has great difficulty handling a complex logic function requiring up to 16 p-terms. One prior art solution was to handle the 16 p-term function in two stages. The outputs of two 8 p-term functions are first determined and later combined. The combination is then fed back as inputs. However, the downside is that speed is sacrificed. In order to get the 16 p-term wide function, the PLD has to be cycled through twice, which results in approximately twice the processing time and requiring three macrocells to be utilized.
Another prior art approach increased flexibility by incorporating more p-terms. The extra p-terms were assigned to the macrocells. Hence, the standard number of p-terms for each macrocell is increased. For example, each macrocell could be designed to handle 16 p-terms.
However, this approach suffers from the fact that silicon die size is directly proportional to the number of p-terms being implemented. Unfortunately, increasing the number of p-terms directly increases the die size by a significant amount. A large die size is highly disadvantageous because less dies can be made from a given silicon wafer. This translates into higher production costs. Furthermore, as the die size becomes relatively large, there is an associated finite delay for the signals to physically propagate through the device. In other words, adding more p-terms detrimentally impacts the overall speed of the device.
Another prior art method for increasing the number of p-terms involves implementing parallel expanders. Parallel expanders have the capability of steering extra p-terms to any macrocell. The extra p-terms made available by the parallel expanders are used to augment the existing fixed number of p-terms for that particular macrocell. However, there is an incremental performance penalty (i.e., reduced speed) associated with adding p-terms via the parallel expanders. Moreover, parallel expander architecture increases the die size.
Therefore, what is needed is a PLD having a relatively low average number of p-terms which also has the capability of handling a large number of p-terms without noticeable performance degradation.